1. Field of the Invention
The present invention relates to semiconductor processing and more particularly to the processing of semiconductor wafers that incorporate small design features using advanced processing techniques employing organic interlevel dielectrics.
2. Description of Related Art
Achieving the requisite adhesion between the innumerable miniaturized components, materials and material layers that constitute today""s high-density multi-level semiconductor integrated circuits presents an ongoing challenge. The failure of various components, materials and material layers to adhere properly at their interface can result in numerous problems in the fabricated integrated circuit. One aspect of semiconductor circuit fabrication thus involves the identification and resolution of such problems.
U.S. Pat. No. 6,174,793 discloses a method for improving adhesion between a copper layer and a diffusion barrier layer made of silicon nitride by providing an intervening copper phosphide layer to promote adhesion therebetween. Similarly, U.S. Pat. No. 6,211,084 discloses a method for promoting adhesion between a copper layer and a diffusion barrier or capping layer of silicon nitride by treating the copper layer with silane or dichlorosilane plasma to form a copper silicide layer thereon prior to depositing the cap layer. U.S. Pat. No. 6,225,210 achieves the same result by depositing the capping layer on the copper layer under high-density plasma conditions, thus roughening the copper layer surface during deposition and promoting adhesion of the capping layer.
U.S. Pat. No. 6,207,554 discloses employing non-oxide compounds such as SiN2, SiC and related compounds of BC, BCN and BN as an adhesion promoter to promote adhesion between adjacent layers of dielectric material. Similarly, U.S. Pat. No. 6,166,439 discloses a variety of adhesion promoters to promote adhesion between different layered dielectric insulating materials. U.S. Pat. Nos. 6,020,029 and 6,120,639 disclose techniques for improving the adhesion between metal and resinous surfaces in an integrated circuit using an adhesion promoter such as an acidic peroxide or a metal and a reducing agent for the metal.
The use of low dielectric constant organic interlevel dielectric materials (low-k organic ILD materials) has become the industry standard. The increasingly demanding requirements relating to submicron integrated circuitry necessitate the use of organic dielectric insulating materials having extremely low dielectric constants.
The fabrication of a typical level of a multi-level semiconductor integrated circuit generally begins with the deposition of a low-k organic ILD material layer on a cap layer that completes a lower level of the device. The ILD is then patterned and etched to form the requisite trenches and vias forming the desired circuitry for that particular level of the device. A metal, typically copper, is then deposited in the trenches and vias formed in the organic ILD to form, for example, wiring lines on that level and conductive interconnections between levels.
It has now been found that via resistance shift often occurs at the liner/under-Cu interface in submicron semiconductor integrated circuits employing low-k organic ILD materials. This phenomenon has also now been determined to result from weak adhesion between the cap layer of a lower level of the device and the low-k organic ILD deposited thereon. Needless to say, it would be advantageous if there were a method for fabricating such devices without encountering the undesirable via resistance shift described above and the resulting problems associated therewith.
An aspect of the present invention is to achieve a semiconductor multi-level wafer structure employing organic ILD materials as interlevel insulating layers, and preferably low-k organic ILD materials, without creating via resistance shift and associated problems as encountered in the prior art fabrication and use of high density multi-level semiconductor circuits employing organic ILD materials.
Another aspect of the present invention provides an oxidized spin-on coating of an adhesion promoter on a cap layer prior to deposition of an organic ILD layer thereon, and preferably a low-k organic ILD layer, to form a thin silicon-dioxide-like layer that promotes adhesion therebetween and eliminates via resistance shift problems that would otherwise occur during thermal cycles of the fabricated integrated circuit.
In accordance with a first embodiment of the present invention, there is provided a method for preventing via resistance shift in an organic interlevel dielectric in a damascene or dual damascene process comprising coating a previously-formed cap layer with a layer of an adhesion promoter; oxidizing the adhesion promoter layer to form a silicon-dioxide-like film layer on the cap layer; and then applying a coating comprising an organic interlevel dielectric to the silicon-dioxide-like film layer.
Preferably, and most advantageously, the organic interlevel dielectric is a low dielectric constant organic interlevel dielectric material (low-k organic ILD material) such as SILK or porous-SILK. Additionally, it is preferable to apply a fresh adhesion promoter layer to the silicon-dioxide-like film layer prior to applying the organic interlevel dielectric thereto.
In accordance with another embodiment of the present invention, there is provided a method for treating an adhesion promoter coating on a cap layer of one level of a multi-level semiconductor substrate, the method including oxidizing the adhesion promoter layer to form a silicon-dioxide-like film layer on the cap layer by subjecting the adhesion promoter layer to an O2 plasma treatment. In a preferred embodiment, the plasma treatment utilizes O2/N2H2 inductively-coupled downstream plasma (ICP) provided under specific preferred conditions.